Intel’s “Tick-Tock” procedure, where each “tick” representing a die psychologist was followed up by a “tock” representing another microarchitecture, served the organization well for a decent decade before being supplanted with an alternate approach in 2016.
But has Intel abandoned its new methodology so as to go up against AMD‘s up and coming Ryzen silicon?
Intel’s new approach was a three-pronged methodology called “Handle Architecture-Optimization,” and Kaby Lake chips are a result of this technique, being an “Advancement” of the Skylake “Design” and the “Procedure” of Broadwell. The thought was that Intel could press three generations of processors from a solitary architecture.
Or that was the arrangement.
But the declaration a week ago that Intel would launch eighth generation chips codenamed Coffee Lake which depend on 14-nanometer engineering, rather than the expected 10-nanomenter design (codenamed Cannon Lake) proposes that the “Procedure Architecture-Optimization” technique may as of now be relinquished as Intel reuses the architecture for a fourth time.
It’s doubly intriguing given that both a year ago and this year, Intel denied speculations that the 10-nanometer architecture would be postponed. Truth be told, speculations that Intel was experiencing difficulty with its 10-nanometer die shrink date go back to 2015.
Despite Intel apparently surrendering the “Procedure Architecture-Optimization” system at the primary obstacle, the new Coffee Lake chips are still anticipated that would create a 15 percent performance boost over its antecedent, despite the fact that it is not clear whether this alludes to desktop or phone chips.
Remember that Intel guaranteed a comparable hop amongst Skylake and Kaby Lake, and this emerged for desktop chips, and the performance lift was down to clock speed and not directions per clock.
While Intel is being tight-lipped about what’s happening here, the general terms are truly evident – Intel needs new chips to go up against AMD‘s forthcoming Ryzen chips, yet 10-nanometer Cannon Lake silicon isn’t yet prepared, so Intel is compelled to crush another iteration out of the 14-nanometer design.
Furthermore, this won’t not be the last time. As the designs get better, making the jumps will be more troublesome, and if Intel is experiencing issues transitioning from 14-nanometer to 10-nanometer, future die shrinks will be similarly – if not more – precarious.